`timescale 1ns/1ps
`default_nettype none
module pc (
    input  wire        clk,
    input  wire        rstn,     // active-low, synchronous
    input  wire        en,      // =0 时保持不变（用于插泡时冻结IF）
    output reg  [31:0] pc_q
);
    always @(posedge clk) begin
        if (!rstn) pc_q <= 32'h0000_0000;
        else if (en)     pc_q <= pc_q + 32'd4;
        else             pc_q <= pc_q;  // hold
    end
endmodule

